Low-power PLDs: a good choice for portable designs

Today, anyone currently designing portable equipment is concerned with power, cost, and package size. These concerns usually rule out traditional silicon solutions employed by telecom, datacom and server engineers, since a speed/power tradeoff often exists. For portable designers, this usually excludes programmable logic as well. Moreover, sense amplifier technology and large packages has left little chance of these devices appearing in portable applications.

These restrictions are now changing based on a growing acceptance of low-power programmable logic devices (PLDs) appearing in an increasing number of portable applications. This trend is lead by the handset industry where increased volume has reduced average selling prices and programmable logic has been successfully deployed to reduce power, and add differentiating features.

Easy to use

Multiple uses for low-power programmable logic are evident in today’s portable applications. Common applications include I/O expansion, power on sequencing, data conversion and discrete logic functions. Low-power PLDs also easily incorporate new features that make them easy to use and more versatile than standard logic solutions. For example, if a design change or a timing anomaly occurs during prototype build, it is much easier to remedy in a hardware description language rather than by adding jumpers to a printed circuit board. With easyto- use software, designs changes are readily made and normally do not require a layout re-spin.

Sleep modes are used by micro controllers to reduce power consumption by ‘turning off’ certain parts of the device. In select low-power PLDs this is accomplished through a stop gate that disables any or all inputs to the device. By disabling the input, all internal signals connected to that input also stop, thus reducing power consumption. The stop gate can then be released to resume normal operation. This is useful when the duty cycle of a certain circuit is not 100 percent and may be shut down for a specified period of time. Some low-power PLDs also have the added feature of input hysteresis on a pin-by-pin basis, easing troublesome false signalling due to a noisy environment, or signal inputs that may have non-linear transitions. This feature works well when interfacing to slow transitioning input signals.

Other key features of low power PLDs include clock division and clock doubling. Multiple clock domains may be implemented in the PLD, decreasing the number of external oscillators, thereby saving component costs. Using a clock multiplier (2X), flip-flop toggle speeds will match the incoming clock speed with extremely low clock latency. This yields faster conversion rates, better resolution of pulse widths and, when combined with a clock divider, multiple frequency domains. With the inherent advantages of modern low-power PLDs, these features can greatly help attain project goals.

What is the real cost?

As a result of more efficient process technologies, new generations of low-power PLDs are now available that offer even lower cost points. Today’s low-power PLDs are priced competitively with SPLDs, and offer significantly greater resources. Depending on the scale of complexity, a simple 8 input logic function or actually performing data conversion, choices can widely vary. For a simple 1.8 volt single positive edge triggered D-type flip flop with clear and preset (74AUC74), the cost is approximately $0.48 (1k units) and is equivalent to 1 macro cell of a 32 macro cell CPLD (See Table 1).

Power consumption, depending on clock rate, is also in favour of the single-component logic solution. For a simple logic function, a single discrete device is the best solution from a power and price standpoint.

Situations exist where discrete logic functions and data conversion are both involved. For instance, consider a simple parallel to serial conversion with a counter. An example of this function in discrete logic is a generic 74LV164A 8-bit serial in parallel out shift register and a 74LV163A 4-bit synchronous binary counter. Examination of power consumption shows that, in this case, the maximum static power consumption is 20uA. For a 4-bit counter, maximum static power consumption is 20uA. Average costs for the discrete devices (1000 unit) mentioned are $0.44 and $0.48 respectively, while pin counts for each device range from 14 to 20 pins. For 3.3 or 2.5-volt devices, prices are reasonably inexpensive. At 1.5 volts or 1.8 volt, the price more than doubles for 1000 unit pricing. Low-power, discrete logic families are available, but have limited device selection and higher cost.

When compared with a low power PLD, the cost is $1.00 (US), and the maximum static power consumption is 90uA, although typical standby is 16uA. As for pin count, a 32-macrocell device comes in packages that range from 32 (QFG32) to 44 (VQ44) pins. One very important fact is that these functions (counter and conversion) in a low-power, PLD use only a small portion of available logic resources.

When to consider low-power PLDs

Why should a designer consider using low-power PLDs over alternative solutions? It is important to consider potential design solutions and rank the importance of each benefit. There are other possible choices for logic designs, including ASIC and ASSP devices, however as non recurring engineering (NRE) charges continue to climb and time to market pressures increase, these devices may be prohibitive for quantities below 250k units per year. A list of design priorities, such as power consumption, board space, routing resources, availability, schedules and cost, must be considered.

From a power perspective, PLDs incorporate features to reduce dynamic power consumption by making use of sleep modes, or reducing internal clock frequencies using clock division. From a performance point of view, edge detecting the incoming clock to the flipflop and toggling the flip-flop at twice the speed, is a method of doubling performance without doubling the power consumption. And, if board space is critical, a single device and its associated routing resources requires far less space than using two, three or four devices to achieve the same functionality.

Programmability also offers the opportunity for last minute design changes. If timing or logic changes need to be implemented after a prototype build, it is simple to update the design file, simulate the change, and make sure the modification accomplishes the goal through timing verification. If discrete logic is used, jumper wires are used, but timing may not prove to be an easy task. When PCB traces are changed, timing problems may occur. By keeping logic changes within a single device, it is almost guaranteed that the design will work through simulation.

Some PLDs also offer input pin hysteresis. This feature can be enabled on a pin-by-pin basis through software settings. If a design is placed into a noisy environment, and the supply voltage is low (1.8v or below), signals may be affected by external EMI or RFI. Large motors, transformers or lightning can affect a design depending on its operating frequency. Reprogrammability offers designers the ability to turn on hysteresis, thus preventing intermittent failures without changing the circuit design. The design can also be recompiled using input hysteresis as download and test, to check for additional intermittent failures.

PLDs also offer voltage and I/O standards translation. Due to cost pressures, legacy parts, and the need to preserve intellectual property, system designers often run into tradeoffs when selecting a lower cost product to save money, then faced with the problem of supply voltage or I/O signalling incompatibility. By using programmable logic, designers can choose the voltage for a specific number of I/O, including the JEDEC switching standard, and seamlessly match these to legacy products in a single device. This makes cost reduction and feature enhancement less cumbersome to implement.

There are many other features programmable logic offers that standard fixed logic cannot, including different output pin settings such as open drain, weak pull-ups, bus keeper and using pins as programmable grounds. These settings help ease interface issues on a variety of different devices. Open drain configurations offer the ability to communicate bi-directionally on a single wire on bus structures such as SMBus and I2C. Bus keeper circuits may eliminate discrete bus buffers or transceivers. The use of programmable grounds is usually helpful in situations where noise immunity is critical. Designers reduce the chances of false triggering by setting a programmable ground pin on either side of a signal that is susceptible to noise.

Low-power PLDs are available in multiple package types including generic SOIC, chip scale, ball grid arrays and low-cost micro lead frame, also known as quad flat no-lead packages. Pb free packaging is available where required. Automotive grade PLDs are also available to address the industry’s need for traceability and higher quality standards. This broad range of packages, including migration to larger or smaller device, makes low-power PLDs a good choice for a variety of design requirements.


Designers should look further when implementing logic functions in portable designs. Cost savings, board area, power consumption and performance when using more than two or three discrete logic devices, are in favour of low-power, programmable logic. However, the intangible benefits of reprogrammability may further outweigh the initial cost. Low-power PLDs provide a minimal chip-count solution and single piece stocking, alleviating the need to stock multiple devices. There is also no obsolescence or long procurement cycle worries since PLDs can adapt to many different applications. Today’s PLD suppliers also provide a complete suite of intelligent software tools required to implement the design and generally, many are provided at no cost and are often already in use by contract manufacturers. Programmable logic providers also offer valuable application notes and free VHDL code for a vast array of applications. Low cost design kits are also available to evaluate a design prior to implementation.

Advanced power loss analysis using oscilloscope

The higher data speeds and GHz-class processors used in new Switch Mode Power Supply (SMPS) architectures are creating new pressures for power supply designers. To address these demands, designers are adopting new techniques like synchronous rectifiers, active power filter correction and higher switching frequencies.

However, these techniques bring unique challenges such as high power dissipation at the switching device, thermal runaway and excessive EMI/EMC. During the transition from an “off” to an “on” state, the power supply experiences higher power loss. The inductors and transformers isolate the output voltage, smooth the load current and are subjected to switching frequencies. This results in power dissipation and occasional malfunctioning because of saturation.

The measurement of power loss at the switching device and inductor/transformer assumes great importance because the power dissipated in an SMPS determines the thermal effect on the power supply and its overall efficiency.

Accurate power loss measurement
The MOSFET power transistor, driven by a 40kHz clock, controls the current. The MOSFET in Figure 1 is not connected to the AC main ground or to the circuit output ground. Hence, taking a simple ground referenced voltage measurement with the oscilloscope would be impossible because connecting the probe’s ground lead to any of the MOSFET’s terminals would short-circuit that point to ground through the oscilloscope.

Making a differential measurement is the best way to measure the MOSFET’s voltage waveforms. With a differential measurement, you can measure VDS—the voltage across the MOSFET’s drain and source terminals. VDS can ride on top of a voltage ranging from tens to hundreds of volts, depending on the range of the power supply.

There are several methods to measure VDS:

• Float the oscilloscope’s chassis ground. This is not recommended because it is unsafe for the user, the device under test (DUT) and oscilloscope.
• Use quasi-differential measurement, employ two conventional passive probes with their ground leads connected to each other and use the oscilloscope’s channel math capability. However, the passive probes, in combination with the oscilloscope’s amplifier, lack the CMRR to block any common mode voltages adequately.
• Use a commercially available probe isolator to isolate the oscilloscope’s chassis ground. The probe’s ground lead will no longer be at ground potential, and you can connect the probe directly to a test point. Probe isolators are effective but are more expensive than differential probes.
• Use a true differential probe on a wideband oscilloscope which allows the accurate measurement of VDS.

For current measurements through the MOSFET, clamp on the current probe then finetune the measurement system. Many differential probes have built-in DC offset trimmers. With the DUT turned off and the oscilloscope and probes fully warmed, set the oscilloscope to measure the mean of voltage and current waveforms. Use sensitivity settings that will be used in the actual measurement. With no signal present, adjust the trimmer to null mean value for each waveform to zero. This step minimizes the chance of a measurement error, which results from quiescent voltages and current in the measurement system.

Correcting errors

Before making any power loss measurement in an SMPS, synchronize the voltage and current signals to eliminate propagation delay. This process is called “deskewing.” The traditional method calls for calculating the skew between the voltage and current signal and then manually adjusting the skew using the oscilloscope’s deskew range. However, this is a tedious process. It is simpler to use a deskew fixture that can be purchased with an oscilloscope. To deskew, connect the differential voltage probe and the current probe to the deskew fixture’s test point. The deskew fixture is driven by either the Auxiliary output or cal-out signal of the oscilloscope.

Measuring the dynamic switching parameter is simple if the emitter or the drain is grounded. On a floating voltage, however, there is a need to measure a differential voltage. A differential probe can be used to accurately characterize and measure a differential switching signal. Hall Effect current probe allows the user to view the current through the switching device without breaking the circuit. By deskewing, the propagation delay caused by the probes is eliminated.

The next step is to compute the power waveform and measure minimum, maximum and average power loss at the switching device for the acquired data. Knowing power loss at turn on and turn off enables you to work on voltages and current transitions to reduce the power loss. During the load change, the control loop of SMPS changes the switching frequency to drive the output load.

In a real-world environment, the power supply is continuously subjected to a dynamic load. It is important to capture the entire load-changing event and characterize the switching loss to make sure it does not stress the device. Today, most designers use an oscilloscope with deep memory (2MB) and a high sampling rate to capture events in the required resolution. However, this presents the challenge of analyzing a huge amount of data for the switching loss points, which stresses the switching device. The key to solving this challenge is choosing the application-focused software that automates the process.

Another way to reduce power dissipation comes in the core area. From the typical AC/ DC and DC/DC circuit diagram, the inductor and transformer are the other components that will dissipate power, thereby affecting power efficiency and causing thermal runaway. Typically, inductors are tested using an LCR meter which utilizes a test signal—the sine wave. In a switched power supply, the inductors will be subjected to high voltage, high current switching signals, which are not sinusoidal.

As a result, power supply designers need to monitor the inductor or transformer behavior in a live power supply. However, testing with LCRs may not reflect a real-life scenario. The most effective method of monitoring the behavior of the core is through the B-H curve because it quickly reveals inductor behavior in a power supply.

The inductor and transformer will have different behavior during the turn on time and steady state of the power supply. In the past, to view and analyze B-H characteristics, designers had to acquire the signals and conduct further analysis on a PC. With modern oscilloscopes and power measurement software, users can do the B-H analysis directly on the instrument giving them an instantaneous view of inductor behavior.