# Predict loop gain in buck converters

Stability is a critical issue in designing DC/DC converters. The stability of a buck converter (Figure 1) is determined by the feedback loop compensator GCOM and the output power filter GLC. Nowadays, most PMIC manufacturers provide internal or external compensators, which are optimized for specific values of inductors and capacitors in the output power filters. However, the output power filters may need to be redesigned according to the converter specifications or due to concerns regarding cost and packaging. With a given compensator, changing the output power filter may considerably affect the stability of a buck converter. Finding an accurate method for evaluating system stability with the redesigned output filter becomes crucial in a buck converter design.

Loop gain is a powerful tool for system stability analysis. Figure 2 shows the bode plot of a buck converter loop gain with crossover frequency of 70 kHz. The phase margin is about 70°, which indicates that this is a stable high-performance converter. Prediction of the loop gain for the redesigned output power filter can indicate the stability of the new converter.

One approach to predicting the loop gain involves empirical methods. The empirical method depends mostly on experience, and it normally gives the designer a rough estimation. Another more accurate approach is the use of simulations. With an accurate model, the simulation method can predict the loop gain with very high accuracy. However, a big challenge associated with this method is how to obtain an accurate model. In most cases, a lot of time and analysis are required to fine-tune the model parameters for all components, especially the PMICs. Therefore, using simulations is not an ideal method due to the time-consuming nature of the process.

An approach combining laboratory measurements and systematic analysis is proposed to predict the loop gain for a buck converter. This approach requires only a few measurements and some straightforward analysis. It is more accurate than the empirical method and requires less time compared to the simulation method. Moreover, unlike the simulation method, this approach doesn’t require special software such as Pspice or SIMetrix/SIMPLIS. All the analysis and calculations can be implemented with Microsoft Office Excel. The proposed approach saves valuable engineering time in stability analysis and provides good guidelines for component selection.

**Prediction approach**

In a buck converter, most blocks are linear, such as the output power filter GLC, feedback voltage attenuator GFB, error amplifier GEA and compensator GCOM. Meanwhile, the switching circuit GSW and the pulse width modulator (PWM) GMOD are nonlinear. Since stability analysis only focuses on the frequencies below the switching frequency, an average model can be used to linearise the switching circuit and the PWM.

With the average model, the entire converter can be modeled as a linear system within the interested frequency range. Thus, Thevenin’s theorem can be used to simplify all linear blocks, except the output filter, as seen in the Thevenin equivalent circuits (Figure 3). The equivalent circuit consists of a voltage source Vs(f) in series with an impedance Zs(f). The denotation (f) indicates that the voltage and impedance value vary with the frequencies. Once the Thevenin equivalent circuit is known, the output voltage Vout can be calculated in a straightforward manner. With the voltage divider principle, the loop gain can be obtained.

Measurements with a network analyser are used to derive the Thevenin equivalent circuit. The network analyzer is widely used to measure the loop gain for a buck converter. Figure 4 shows a typical set-up of loop gain measurement. In this set-up, the network analyzer injects a sweeping-frequency AC signal into the converter through a small resistor Rinj. Its input channel R measures the injected signal Vr(f), and its input channel A measures the output signal Vout(f). The ratio A/R represents the loop gain T(f) of the converter. T(f) can be rewritten in equation 1.

Ta(f) can be expressed with the output capacitor impedance ZC(f) and the entire output filter impedance ZLC(f) as:

Ta(f) = VOUT (f) / VSW (f) = ZC (f) / ZLC (f)

Note that the load impedance Zload is neglected, since in most cases Zload is considerably larger than ZC.

Tb(f) is expressed with the impedance ZLC(f), Thevenin equivalent voltage VS(f) and impedance ZS(f) as:

Tb(f)= VSW (f) / Vr (f) = VS (f) / Vr (f) . VSW (f) / VS (f)

= VSW (f) / Vr (f) . { ZLC (f) / ZS (f)+ZLC (f) }

ZC(f) and ZLC(f) in Equations 2 and 3 are well-known. If VS(f)/ Vr(f) and ZS(f) are also found, the loop gain T(f) can then be predicted with Equations 1, 2 and 3.

The two unknowns, VS(f)/ Vr(f) and ZS(f), require two equations to solve. The two equations are obtained with network analyzer measurements using two different output filters ZLC1(f) and ZLC2(f). In this prediction approach, R channel of the network analyzer still measures the injected voltage Vr(f), while it’s a channel measures the switching node voltage Vsw(f) (Figure 5).

With the measured ratio VSW1(f) / Vr(f) (or Tb1(f)) and VSW2(f)/ Vr(f) (or Tb2(f)), the two unknowns VS(f)/ Vr(f) and Zs(f) can be solved. Then, the loop gain can be obtained for any output power filter with Equations 1, 2 and 3.

**Proposed steps**

The concept of the proposed prediction approach has been introduced. The detailed procedures are explained in the following steps:

Step 1. Obtain the first equation for the two unknowns, VS(f)/ Vr(f) and ZS(f).

The inductor L and output capacitor C are selected as the values specified with the optimized compensator provided by the PMIC manufacturer. The output filter impedance can be calculated as:

ZLC1 (f) = j2πfL1+DCR1 + ( 1/j2πfC1+ ESR1)

Where L1 is the inductance of the inductor, DCR1 is DCR of the inductor, C1 is the capacitance of the output capacitor, and ESR1 is ESR of the capacitor.

A network analyser is used to measure the ratio VSW1(f)/ Vr(f) (or Tb1(f)),

Tb1 (f) = 10 Gain-Tb1 (f) / 20 . e i Phase-Tb1(f)

where Gain_Tb1(f ) is the logarithmic gain of Tb1(f ) and Phase_Tb1(f ) is the phase shift of Tb1(f ).

The first equation is obtained by substituting Equations 4 and 5 into Equation 3,

Tb1 (f) = Vs (f) / Vr (f) . { ZLC1 (f) / Zs (f) + ZLC1 (f) }

Step 2. Repeat step 1 with different values of inductor and capacitor to get the second equation for the two unknowns.

The inductor and capacitor are changed to larger values, such as twice of L1 and twice of C1. The new parameters are L2, DCR2, C2 and ESR2. The output filter impedance can be calculated as:

ZLC2 (f) = j2πfL2+DCR2 + ( 1/j2πfC2+ ESR2)

Tb2(f) is obtained with the same measurement as described in Step 1:

Tb2 (f) = 10 Gain_Tb2 (f) / 20 . e i Phase_Tb2 (f)

The second equation to solve VS(f)/ Vr(f) and Zs(f) is obtained by substituting Equations 7 and 8 into Equation 3:

Tb2 (f) = Vs (f) / Vr (f) . { ZLC2 (f) / Zs (f) + ZLC2 (f) }

Step 3. Solve the two unknowns VS (f)/ Vr (f) and Zs (f). Two equations for the two un- known’s have been obtained from Step 1 and Step 2. So, Vs(f)/Vr(f) and Zs(f) can be solved as:

Zs (f) = ZLC1 (f) . ZLC2 (f) . { (Tb2(f) _ Tb1(f) } / Tb1(f) . ZLC2 (f) _ (Tb2(f) . ZLC1 (f)

Vs (f)/Vr (f) = Tb1(f) + Tb1(f) . Zs(f) / ZLC1(f)

Step 4. Predict the loop gain. The inductor and capacitor are redesigned according to the converter specifications, such as the maximum inductor current ripple, the maximum output voltage ripple, the maximum component height, and so on. Assume that their parameters are L3, DCR3, C3 and ESR3. The output filter impedance can be calculated as:

ZLC3 (f) = j2πfL3+DCR3 + ( 1/j2πfC3+ ESR3)

And the output capacitor impedance is:

ZC3 (f) = ( 1/j2πfC3+ ESR3)

From Equations 1, 2 and 3, the loop gain can be rewritten as:

T(f) = Ta(f) . Tb(f)

= Zc3(f)/ZLc3(f) . { Vs(f)/Vr(f) . ZLc3(f) / ZLc3(f) + Zs(f) }

=Vs(f) / Vr(f) . Zc3(f) / ZLc3(f) + Zs(f)

Vs(f)/Vr(f) and Zs(f) have been solved in Step 3. Zc3(f) and ZLC3(f) are known. Therefore, the loop gain T(f) can be predicted with Equation 14.

**Approach demonstration**

Micrel’s MIC2159, a 400kHz synchronous buck controller, is used as an example to demonstrate the proposed prediction approach. Figure 6 shows a buck converter using a MIC2159 controller.

Step 1: The inductor and capacitor in the output power filter are selected as: L1 = 9μH, DCR = 50mΩ, C1 = 330μF, and ESR1 = 45mΩ. Then the impedance ZLC1(f) is:

ZLC1(f)= j2πfL1 + DCR1 + (1/j2πC1 + ESR1)( Ω)

Tb1(f), or VSW1(f)/ Vr(f), is measured with a network analyser. The gain and phase of Tb1(f) are illustrated in Figure 7.

Step 2: Repeat step 1 with different inductor and capacitor: L2 = 19μH, DCR2 = 99mΩ, C2 = 550μF, ESR2 = 24mΩ the impedance ZLC2 (f) is:

ZLC2 (f) = j2πfL2 + DCR2 + (1/j2πC2 + ESR2)( Ω)

The gain and phase of Tb2(f) is shown in Figure 8.

Step 3. Solve the two unknowns VS(f)/ Vr(f) and Zs(f) with Equations 10 and 11.

Step 4. Redesign the output power filter and predict the new loop gain using Equation 14. Two different sets of the inductor and output capacitor are used to verify the accuracy of the proposed prediction approach. In case 1, L3 = 13μH, DCR3 = 66mΩ,C3 = 220μF and ESR3 = 50mΩ. In case 2, L3 = 0.99μH, DCr3 = 10.2mΩ, C3 = 300μF and ESR3 = 22.5mΩ. With the proposed method, the loop gain can be easily predicted. Figures 9 and 10 show the predicted loop gain vs. the measured loop gain in cases 1 and 2, respectively. The predicted loop gain matches very well with the measurement results.

In this article, an accurate and fast approach to predicting the loop gain with different output power filters for the buck converter was discussed. This approach requires only two closed-loop measurements using a network analyser and a few algebraic calculations. In doing so, designers can then predict the loop gain for any output power filter by putting the inductor and capacitor parameters into one algebraic formula. Compared with simulation and empirical methods, this approach takes less time and is more accurate. An example using the MIC2159 showed the procedures and accuracy of this prediction approach.

# Save energy with next-generation IGBTs

Worldwide demand for electrical energy has been growing year by year. Rising energy costs, the need to reduce the greenhouse effect caused by CO2 emissions, and the expectation of limited availability of fossil energy resources in the future all require responsible use of these resources for energy savings. Potentially, large energy saving can be seen in connection with numerous industrial applications, for example, drive engineering or power supply systems. Drive engineering energy consumption can be reduced by using state of the-art and efficient inverters for machines.

For this ever-growing market of applications with the latest efficient inverters, special optimized types of power semiconductors are needed. The new 1200V IGBT4 generation combined with improved emitter control diodes from Infineon provides three optimized chip versions for low-, medium- and high-power IGBT modules that are designed for the needs of modern inverter concepts for different applications.

These three optimized chip versions are the IGBT4-T4 chip with fast switching behaviour for low-power modules with Inom=10-300A; the IGBT4-E4 chip with good switching and on state characteristics for medium power modules with Inom=150-1000A; and the IGBT4-P4 chip with soft switching behaviour for high power modules with Inom > 900A.

The P4 version has been extensively described in other reports, so this article focuses on the low- and the mediumpower versions.

Two criteria for success during the development of a new chip generation are low static and dynamic losses. The electrical performance of the new IGBT4 generation is better than the previous IGBT3 generation. The new 1,200V IGBT4 power semiconductor generation allows a maximum operation temperature of Tvjop=150°C—compared with the operation temperature of 125°C of the previous generation. For the first time, Infineon introduced a maximum operation temperature of 150°C at 600V power semiconductors of the third generation. This higher operation temperature results in the potential of higher output power by use of the full temperature swing under the same cooling conditions.

Additionally, the optimization of the assembly technology shows a noteworthy power cycling (PC) improvement. This ensures at least the same PC lifetime expectation and higher output current because of the increased operation temperature—or enhanced lifetime at comparable output power as can be chosen by the user.

**IGBT behaviour**

However, these advantages are not enough. The switching characteristic of the device itself is also an important issue. Since the IGBT3 family is already soft enough for nearly all low- and medium-power applications, a further objective of IGBT4 development was a comparable softness with the corresponding IGBT3 types. Switching losses are a function of the external gate resistor. The turn off losses do not depend on Rg for a wide range of gate resistors, which can be explained by intrinsic switching of the IGBT.

The stray inductance in combination with the current gradient has an influence on the voltage characteristic during turn on and turn off as dv=Ls * di/dt. Thus, the over voltage increases when switching off with larger Ls.

Aside from the turn off losses, the softness of the IGBT is also quite insensitive to the gate resistance. The switching performance was compared at nominal current as a function of the DC link voltage.

The IGBT4-T4 is slightly softer than the low power IGBT3-T3 chip, and the IGBT-E4 version is slightly softer than the medium power IGBT3-E3 chip. As designed, the E versions are softer than the T series. Thus, it is possible to turn off an E4 at higher DC link voltage and/or connected to higher inductance.

More importantly, the turn off becomes snappier with increased Ls. Therefore, it is surely very reassuring that the tested 300A IGBT4-E4 shows soft turn off in spite of a stray inductance of the DC link busbar of 65nH and a DC link voltage of 900V.

The diode behaviour as a function of the stray inductance also has to be considered during the selection of an optimal IGBT for a particular application. In the example described, the switching losses and the softness of the used emitter controlled high efficiency diode show a negligible dependence on the increased stray inductance.

However, if a high DC link voltage is combined with an increased stray inductance it is necessary to reduce the switching speed during turn on by increasing the external turn on gate resistor to achieve soft diode switching.

An increased external gate resistance results in higher turn on losses. Increased stray inductance reduces the softness of IGBTs and diodes that offers an optimization potential for all IGBT modules.

**Iposim calculations**

In order to evaluate the operation of the new components in an inverter mode, the loss characteristic was calculated by using Infineon’s calculation software tool Iposim. Iposim only needs to be fed with the static and dynamic losses as well as the thermal data and the ambient temperature.

As one solution, the highest possible RMS current as a function of the junction temperature and the switching frequency was calculated. The calculation for an IGBT in a 62mm half bridge module shows that the new chip family yields higher output currents in direct comparison to the former chip generation at 125°C. Furthermore, it’s possible to increase the output current of the same component by up to 17 percent if it is possible to use the higher operation junction temperature of 150°C permitted in the application.

In a further Iposim calculation, the new and the current generation were compared. In a first step the maximum Irms of an E3 was calculated for 8kHz with the junction temperature of 125°C. In the next step, the losses for the same inverter output current for all other chip versions were investigated.

The module losses of an E4 module are approximately 3 percent lower than for the E3 chip and comparable to the T3. Compared to the E4 the losses of a T4 are reduced by approximately 3 percent.

The new power semiconductor generation has been optimized to improve its characteristics and to increase the output power of the inverter as a consequence of the increased operation temperature of Tvjop = 150°C.

In case of Tvjop = 125°C the new IGBT generation offers reduced total losses by up to 6 percent.

An optimization of the assembly technology furthermore ensures the same lifetime expectation and approximately 17 percent more output current as a consequence of the increased operation temperature—or enhanced lifetime at comparable output power as can be chosen by the customer.

# Understanding non-linear slope compensation: a graphical analysis

Evaluating peak CMC waveforms Let’s assume a typical application where Vout and L are fixed, and determine how the value of Vin affects slope compensation. Analysing the problem with time plots of steady-state inductor and control signals provides us with a good vehicle for visualizing the operation of slope compensation in specific applications.

In Figure 11, the inductor current waveforms are shown for three values of Vin. Note that the downward slope of the inductor current, Sd, is constant for a fixed value of inductor and Vout, independent of Vin. The dotted lines represent the values of (Icontrol – Islope) referenced to their respective inductor current waveform. Any change in Iload causes this cluster of waveforms to simply shift together up or down.

There is no apparent change in these waveforms within the CMC loop with Iload. However, the load does have an effect on the converter’s output pole and the overall gain of the CMC modulator. These two parameters are components that enter into the overall compensation of the system loop. The waveforms in Fig. 11 assume a low value of linear slope compensation. The downward slope of (Icontrol – Islope), Se, is of significantly lower magnitude than Sd. From the previous series of plots illustrating the settling of perturbed current, it is probable that the Vin = 3 condition will be unstable with this low level of slope compensation.

Also note that, with this low value of Se, a small disruption of the control signal results in relatively large change of duty cycle. Greater Se therefore results in much lower system sensitivity to injected noise.

We assume the same set of operating conditions in Fig. 12. Here, Se is greater. This illustrates a special case of slope compensation. The slope of Se is equal to one half of the downward slope of the inductor current. The three (Icontrol – Islope) waveforms nearly lie on top of each other. That is, changes in Vin, which result in a simultaneous change of duty cycle and peak inductor current, require no change in the (Icontrol – Islope) signal.

Thus no change is required in the error amplifier’s output or feedback or control voltage. There is no systematic source of line-regulation error, even with finite error amp gain. Also note Se/Sd = 0.5 is the minimum value of Se that assures stability for all duty cycles.

Another special value for slope compensation is observed in Fig. 3. Here we have Se/Sd = 1, and the special case of ‘deadbeat’ is achieved for all values of Vin.

Because the slope of (Icontrol – Islope) matches the downward slope of the inductor current, the inductor current will recover from a disruption at the first PWM termination. The inductor’s downward slope will instantaneously align to the desired steady state value. For linear slope compensation, if deadbeat is achieved for a particular Vout and L, it is achieved for all values of Vin.

Let’s increase the downward slope (Fig. 4). The general trend is that the magnitude of the control current, i.e., the value of (Icontrol – Islope) at the start of the switch cycle, must increase as Se increases. The drawback is the dynamic range of the control is compressed towards the high end of the signals’ range. No additional benefit in stability is gained with excessive Se. In fact, in the extreme, the loop approaches a hysteretic mode of operation and the benefits of CMC are lost.

Next, we plot the same current waveforms for the same series of set applications (fixed output voltages) for non-linear slope compensation (Fig. 5). Ideally, Se changes linearly with duty cycle as Vout is changed so a more constant Se/Sd ratio is maintained with change in Vout. The magnitude of Islope is derived by integrating this ideal Se which is a linear function of duty cycle. So the resultant non-linear Islope increases with the square of the duty cycle before it is subtracted from Icontrol.

In Fig. 5, a low value of nonlinear slope compensation is applied and all of the observations discussed in reference to Fig. 1, where a low value of linear slope compensation is applied, still hold true. Instability will probably occur for Vin = 3 because this level of Se is marginal compensation for higher values of duty cycle. The sensitivity to noise is still greater than that for larger Se. Therefore these waveforms represent an inadequate level of slope compensation.

The waveforms in Fig. 6 have the appearance of no change in (Icontrol – Islope) for the full range of Vin related duty cycles and is similar to the example in Fig. 12 for linear slope compensation and Se/Sd = 0.5, set at the midpoint of the Vin and Vout ranges. The locus of peak currents for all values of Vin is linear and therefore the non-linear slope compensation seen in Fig. 16 is only an approximation of zero line regulation. However for this range of Vin (3 to 5.5 volts), the approximation of zero line regulation is close to ideal.

The deadbeat condition for non-linear slope compensation is only met for one value of Vin. Figure 7 illustrates a slight deviation of the Se = Sd criteria for deadbeat at the high and low values of Vin. Linear compensation maintains deadbeat over Vin, however non-linear will be shown to be superior to linear when the effect of slope compensation is examined over the range of possible Vout values.

In Fig. 8, we take a final look at the same three values of Vin for non-linear slope compensation with a high value of Se. One advantage of non-linear slope compensation for high duty cycles and high Se is that the peak magnitude of Icontrol is less than in the linear case and therefore provides more dynamic range of the control signal and less opportunity for over-ranging Icontrol.

From this last series of plots where Vin is varied for a fixed value of Vout, we see the case for zero line regulation and the case for deadbeat over the full range of Vin is less than ideal for nonlinear slope compensation and theoretically ideal for linear slope compensation. This section addresses the full range of Vin for one particular Vout. The argument for non-linear slope compensation requires reviewing the Se controlled parameters for the full range of Vout applications.

Linear vs. non-linear slope compensation over the full range Current-mode control (CMC) acts as a sampling function. Detailed analysis of CMC sampling results in a complex pole pair located at one half of the switching frequency. Unlike the complex LC pole pair of voltage mode control, the CMC sampling poles are always at one half of the switching frequency and cannot drift down with component selection. All complex pole pairs do have the danger of excessive gain peaking and rapid phase shift if not managed properly. Q is the common term for qualifying the amount of gain peaking. For example, a Q of 1.5 indicates that the gain will peak by 50 percent near the pole frequency. High values of Q even at one half of the switching frequency can introduce instability into the system loop and therefore peaking is managed by the amount of slope compensation added to t he CMC loop. The term Qs is used to identify the peaking associated with the CMC sampling complex pair pole.

The value of slope compensation is one of many degrees of freedom effecting stability, or instability. The end users’ ability to adjust Se complicates the implementation of the peak CMC integrated controller circuit. Therefore user cannot usually adjust the magnitude of peak CMC Se.

It is simpler if the controller IC provides the most robust fixed value of slope compensation that best covers the full range of applications. Good engineering practice d suggests that a fixed value of Se be set at some ideal value near the centre of the application space. As the same design is applied over the full range of rated Vout, deviations in parameters such as Icontrol dynamic range, line regulation, Iripple, and Qs are balanced at the extreme limits of both Vout and Vin. The following plots compare linear and non-linear slope compensation operation at typical high and low settings for Vout. Examples of typical 5- and 16- volt rated converters are used for the analysis.

Figure 19 is useful for visualizing the concept of application ‘space’ for a buck DC/DC power converter. The rated range of Vout and Vin for any DC/DC buck converter is bound by the maximum duty cycle limits along the top boundary, the minimum duty cycle and the value of the error-amp reference voltage along the bottom, and by the minimum and maximum allowed Vin values on the left and the right sides of the box. Within this application space, any value of regulated Vout can be provided with the full range of Vin allowed by the boundaries of the space. In Fig. 9, a typical 5-volt converter application space is defined and three example applications are shown. Each is a constant Vout and the range of Vout represents a majority of the available values of Vout that might be used with the same DC/DC converter model number.

Figure 10 shows the dependence of inductor current ripple on Vin for the three sample applications. Since CMC relies on inductor ripple as a feedback signal, ripple current needs to be bounded. Without enough ripple, excessive noise may interfere with CMC operation and the physical size of the inductor also becomes larger than is necessary.

Excessive current ripple leads to greater output voltage ripple and the possibility of either negative valley current in the inductor or discontinuous conduction if the converter operates with unnecessary discontinuous mode control. A centre value for ripple current equal to 30 per cent of Iload is targeted for this example. It is often desired to limit the deviation of peak-to-peak ripple current from the nominal value over the application’s Vin range. Therefore the analysis assumes that for each application, the target value of ripple is set at the mid level of Vin range. Ripple is adjusted by the selection of the inductor value for a given switching frequency and load current. The ripple’s positive and negative deviation from the target is therefore balanced over the expected range of Vin.

The inductor’s ripple current is not affected by slope compensation. Conversely, the preferred value of slope compensation depends on the system determined inductor ripple; thus the system engineer gets a good idea of the optimal ripple current that best suits the slope compensation value provided by the controller circuit.

The value of ripple current (Fig. 10) for a given Vout is independent of slope compensation design options. Where the type of slope compensation does matter is when it comes to the Qs variation across the vertical direction of the application space and, to a lesser degree, the magnitude variation of the control signal. These parameters are plotted in Fig. 11.

Figure 11 illustrates that across the range of Vout applications, non-linear slope compensation has approximately the same variation in Icontrol as linear slope compensation. The advantage of non-linear slope compensation is the slightly lower peak magnitude required which translates to a larger useful range. This plot assumes Se/Sd = 0.5 at roughly the middle of the application space (Vin = 4 and Vout = 2). A plot of Se/Sd = 1 would look similar, with the curves shifted down by about 0.5 amp. The benefit of non-linear slope compensation is not yet clearly evident with this plot.

Qs is a key parameter in predicting sub-harmonic oscillations. Sub-harmonic oscillation can be predicted by plotting waveforms or by calculating Qs. See the equation for Qs in the Appendix.

It is curious that both largesignal analysis of inductor currents and a small-signal analysis of the CMC gain peaking both predict the sub-harmonic or Fs/2 oscillation. The plots of settling time for perturbed inductor current are a good visual aid for proving instability. However the sampling Qs is a more convenient parameter for plotting a measure of stability as a function of operating conditions.

Figure 12 illustrates the benefit of non-linear slope compensation. For a fair comparison, the magnitude of linear compensation Se at the mid-Vout point is set to match that of non-linear slope compensation the same value of Vin and Vout.

The non-linear slope compensation continuously adapts to change in duty cycle, and so Qs is limited to a narrower band. In the case of linear compensation, Se/Sd deviates from the mid-Vout value as higher values of Vout are selected. Higher Vout applications require higher Se if the ripple current is bounded to a target range.