Low-power PLDs: a good choice for portable designs

Today, anyone currently designing portable equipment is concerned with power, cost, and package size. These concerns usually rule out traditional silicon solutions employed by telecom, datacom and server engineers, since a speed/power tradeoff often exists. For portable designers, this usually excludes programmable logic as well. Moreover, sense amplifier technology and large packages has left little chance of these devices appearing in portable applications.

These restrictions are now changing based on a growing acceptance of low-power programmable logic devices (PLDs) appearing in an increasing number of portable applications. This trend is lead by the handset industry where increased volume has reduced average selling prices and programmable logic has been successfully deployed to reduce power, and add differentiating features.

Easy to use

Multiple uses for low-power programmable logic are evident in today’s portable applications. Common applications include I/O expansion, power on sequencing, data conversion and discrete logic functions. Low-power PLDs also easily incorporate new features that make them easy to use and more versatile than standard logic solutions. For example, if a design change or a timing anomaly occurs during prototype build, it is much easier to remedy in a hardware description language rather than by adding jumpers to a printed circuit board. With easyto- use software, designs changes are readily made and normally do not require a layout re-spin.

Sleep modes are used by micro controllers to reduce power consumption by ‘turning off’ certain parts of the device. In select low-power PLDs this is accomplished through a stop gate that disables any or all inputs to the device. By disabling the input, all internal signals connected to that input also stop, thus reducing power consumption. The stop gate can then be released to resume normal operation. This is useful when the duty cycle of a certain circuit is not 100 percent and may be shut down for a specified period of time. Some low-power PLDs also have the added feature of input hysteresis on a pin-by-pin basis, easing troublesome false signalling due to a noisy environment, or signal inputs that may have non-linear transitions. This feature works well when interfacing to slow transitioning input signals.

Other key features of low power PLDs include clock division and clock doubling. Multiple clock domains may be implemented in the PLD, decreasing the number of external oscillators, thereby saving component costs. Using a clock multiplier (2X), flip-flop toggle speeds will match the incoming clock speed with extremely low clock latency. This yields faster conversion rates, better resolution of pulse widths and, when combined with a clock divider, multiple frequency domains. With the inherent advantages of modern low-power PLDs, these features can greatly help attain project goals.

What is the real cost?

As a result of more efficient process technologies, new generations of low-power PLDs are now available that offer even lower cost points. Today’s low-power PLDs are priced competitively with SPLDs, and offer significantly greater resources. Depending on the scale of complexity, a simple 8 input logic function or actually performing data conversion, choices can widely vary. For a simple 1.8 volt single positive edge triggered D-type flip flop with clear and preset (74AUC74), the cost is approximately $0.48 (1k units) and is equivalent to 1 macro cell of a 32 macro cell CPLD (See Table 1).

Power consumption, depending on clock rate, is also in favour of the single-component logic solution. For a simple logic function, a single discrete device is the best solution from a power and price standpoint.

Situations exist where discrete logic functions and data conversion are both involved. For instance, consider a simple parallel to serial conversion with a counter. An example of this function in discrete logic is a generic 74LV164A 8-bit serial in parallel out shift register and a 74LV163A 4-bit synchronous binary counter. Examination of power consumption shows that, in this case, the maximum static power consumption is 20uA. For a 4-bit counter, maximum static power consumption is 20uA. Average costs for the discrete devices (1000 unit) mentioned are $0.44 and $0.48 respectively, while pin counts for each device range from 14 to 20 pins. For 3.3 or 2.5-volt devices, prices are reasonably inexpensive. At 1.5 volts or 1.8 volt, the price more than doubles for 1000 unit pricing. Low-power, discrete logic families are available, but have limited device selection and higher cost.

When compared with a low power PLD, the cost is $1.00 (US), and the maximum static power consumption is 90uA, although typical standby is 16uA. As for pin count, a 32-macrocell device comes in packages that range from 32 (QFG32) to 44 (VQ44) pins. One very important fact is that these functions (counter and conversion) in a low-power, PLD use only a small portion of available logic resources.

When to consider low-power PLDs

Why should a designer consider using low-power PLDs over alternative solutions? It is important to consider potential design solutions and rank the importance of each benefit. There are other possible choices for logic designs, including ASIC and ASSP devices, however as non recurring engineering (NRE) charges continue to climb and time to market pressures increase, these devices may be prohibitive for quantities below 250k units per year. A list of design priorities, such as power consumption, board space, routing resources, availability, schedules and cost, must be considered.

From a power perspective, PLDs incorporate features to reduce dynamic power consumption by making use of sleep modes, or reducing internal clock frequencies using clock division. From a performance point of view, edge detecting the incoming clock to the flipflop and toggling the flip-flop at twice the speed, is a method of doubling performance without doubling the power consumption. And, if board space is critical, a single device and its associated routing resources requires far less space than using two, three or four devices to achieve the same functionality.

Programmability also offers the opportunity for last minute design changes. If timing or logic changes need to be implemented after a prototype build, it is simple to update the design file, simulate the change, and make sure the modification accomplishes the goal through timing verification. If discrete logic is used, jumper wires are used, but timing may not prove to be an easy task. When PCB traces are changed, timing problems may occur. By keeping logic changes within a single device, it is almost guaranteed that the design will work through simulation.

Some PLDs also offer input pin hysteresis. This feature can be enabled on a pin-by-pin basis through software settings. If a design is placed into a noisy environment, and the supply voltage is low (1.8v or below), signals may be affected by external EMI or RFI. Large motors, transformers or lightning can affect a design depending on its operating frequency. Reprogrammability offers designers the ability to turn on hysteresis, thus preventing intermittent failures without changing the circuit design. The design can also be recompiled using input hysteresis as download and test, to check for additional intermittent failures.

PLDs also offer voltage and I/O standards translation. Due to cost pressures, legacy parts, and the need to preserve intellectual property, system designers often run into tradeoffs when selecting a lower cost product to save money, then faced with the problem of supply voltage or I/O signalling incompatibility. By using programmable logic, designers can choose the voltage for a specific number of I/O, including the JEDEC switching standard, and seamlessly match these to legacy products in a single device. This makes cost reduction and feature enhancement less cumbersome to implement.

There are many other features programmable logic offers that standard fixed logic cannot, including different output pin settings such as open drain, weak pull-ups, bus keeper and using pins as programmable grounds. These settings help ease interface issues on a variety of different devices. Open drain configurations offer the ability to communicate bi-directionally on a single wire on bus structures such as SMBus and I2C. Bus keeper circuits may eliminate discrete bus buffers or transceivers. The use of programmable grounds is usually helpful in situations where noise immunity is critical. Designers reduce the chances of false triggering by setting a programmable ground pin on either side of a signal that is susceptible to noise.

Low-power PLDs are available in multiple package types including generic SOIC, chip scale, ball grid arrays and low-cost micro lead frame, also known as quad flat no-lead packages. Pb free packaging is available where required. Automotive grade PLDs are also available to address the industry’s need for traceability and higher quality standards. This broad range of packages, including migration to larger or smaller device, makes low-power PLDs a good choice for a variety of design requirements.


Designers should look further when implementing logic functions in portable designs. Cost savings, board area, power consumption and performance when using more than two or three discrete logic devices, are in favour of low-power, programmable logic. However, the intangible benefits of reprogrammability may further outweigh the initial cost. Low-power PLDs provide a minimal chip-count solution and single piece stocking, alleviating the need to stock multiple devices. There is also no obsolescence or long procurement cycle worries since PLDs can adapt to many different applications. Today’s PLD suppliers also provide a complete suite of intelligent software tools required to implement the design and generally, many are provided at no cost and are often already in use by contract manufacturers. Programmable logic providers also offer valuable application notes and free VHDL code for a vast array of applications. Low cost design kits are also available to evaluate a design prior to implementation.